1. Field of the Invention
The present invention relates to a sampled data averaging circuit for sampling input data a plurality of times and calculating an average value of the sampled data.
2. Description of the Related Art
A conventional sampled data averaging circuit comprises for example a sampling circuit 1, a data addition circuit 2, a sampling command circuit 3, and a sampled data storage circuit 4, as shown in FIG. 1. Suppose that the number of samplings is 2M, and that a sampled data has a bit width of N bits. The sampling circuit 1 takes as inputs input data D001 with a bit width of N bits and a sampling-start flag S021, and outputs a sampling-completed flag S011 and output data D011 with a bit width of N bits. The input data D001 is data to be sampled, which changes with time.
As shown in FIG. 2, the sampling circuit 1 comprises a counter 11, a comparator 12, N bits' worth of AND circuits 13[0] to 13[N−1], and flip-flops (FFs) 14 and 15[0] to 15[N−1]. The counter 11 begins counting up in response to the rising edge of the sampling start flag S021, and outputs a count value as D111. The counting-up by the counter 11 is halted when the comparison output S111 of the comparator 12 is set as a flag, and the count value is returned to the initial value. The comparator 12 compares the count value D111 of the counter 11 with a fixed value D112, and when the values of D111 and D112 are equal to each other, sets the flag S111. The comparison output S111 of the comparator 12 is output to the AND circuits 13[0] to 13[N−1] and to the FF 14.
The AND circuits 13[0] to 13[N−1] calculate the logical products of the comparison output S111 of the comparator 12 with the N bits of input data D001[0] to D001[N−1], and output the calculated results to the FFs 15[0] to 15[N−1] as data D113[0] to D113[N-1]. 
A clock pulse and a reset pulse are supplied to the FFs 14 and 15[0] to 15[N−1]. The FF 14 captures a value of the comparison output S111 of the comparator 12 in sync with the clock pulse, and outputs the operated results as a sampling-completed flag S011. The FFs 15[0] to 15[N−1] capture and hold the output data D113[0] to D113[N-1] of the AND circuits 13[0] to 13[N−1] in sync with the clock pulse, and output the operated results as data D011[0] to D011[N-1] The D011[0] to D011[N-1] are output data D011 from the sampling circuit 1, that is, sampled data.
As shown in FIG. 3, the data addition circuit 2 has an adder 21 and a selector 22. The adder 21 performs addition of N bits (where N is an integer greater than or equal to 1), adds the N bits of output data D011 of the sampling circuit 1 with N+M bits (where M is an integer greater than or equal to 1) of output data D031 of the sampled data storage circuit 4, and outputs the added result to the selector 22 as data D121. The selector 22 outputs, as N+M bit data D021, one of the output data D031 of the sampling command circuit 3 and the output data D121 of the adder 21, in accordance with the sampling-completed flag S011 from the FF 14. That is, when the sampling-completed flag S011 is 0, the data D031 is output as D021, and when the sampling-completed flag S011 is 1, the data D121 is output as D021.
As shown in FIG. 4, the sampling command circuit 3 has AND circuits 31, 32, a storage circuit 33, a counter 34, and a comparator 35. The AND circuit 31 calculates a logical product of an inverted value of output data S132 from the storage circuit 33 with the sampling-completed flag S011, and outputs the calculated result as data S131 to the storage circuit 33. The storage circuit 33 is a flip-flop, to which the clock pulse and reset pulse are supplied. The storage circuit 33 captures and stores the output data S131 of the AND circuit 31 in sync with the clock pulse, and outputs the operated result as flag data S132.
The counter 34 starts counting-up upon receiving a flag value of the flag data S132, and outputs a count value S133. The counting-up by the counter 11 is halted when a comparison output S135 of the comparator 35 is set as a flag, and the count value is returned to the initial value. The comparator 35 compares the count value S133 of the counter 34 with the fixed value S134, and when S133 and S134 are equal to each other, sets the flag S135. The AND circuit 32 calculates a logical product of the output data S132 of the storage circuit 33 with the inverted value of the comparison result S135 of the comparator 35, and outputs the calculated result as the sampling-start flag S021.
As shown in FIG. 5, the sampled data storage circuit 4 has storage circuits 41[0] to 41[N+M−1] which are flip-flops. The storage circuits 41[0] to 41[N+M−1] are supplied with the clock pulse and reset pulse, and further with the output data D021 (D021[0] to D021[N+M-1]) from the data addition circuit 2. The storage circuits 41[0] to 41[N+M−1] capture and store the data D021[0] to D021[N+M-1] in sync with the clock pulse, and output the operated results as D031[0] to D031[N+M−1].0 The data D031[0] to D031[N+M-1] is the data D031, and the data D031[M] to D031[N+M-1] is an output data D041 of the sampled data averaging circuit.
Next, operation of the conventional sampled data averaging circuit having the above configuration is explained. The input data D001 to the sampling circuit 1 is assumed to change with time, D00A, D00B, D00c . . . , as shown in FIG. 6. In addition to the input data D001, FIG. 6 also shows time charts of the sampling-completed flag S011, sampling-start flag S021, and output data D011 from the sampling circuit 1. At the rising edge of the change from 0 to 1 of the sampling-start flag S021 output from the sampling command circuit 3, the counter 11 begins counting up. When the count value D111 of the counter 11 reaches the fixed value, the output S111 of the comparator 12 changes from 0 to 1, and in response to the change, the input data D001[0] to D001[N-1] at this time is stored, via the AND circuits 13[0] to 13[N−1], in the FFs 15[0] to 15[N−1]. Thus, the output data D011 from the sampling circuit 1 is obtained. Simultaneously with this, the sampling-completed flag S011 output from the FF 14 rises from 0 to 1.
FIG. 7 shows, as time charts, the relations between the sampling-completed flag S011 input to the data addition circuit 2, the output data D011 of the sampling circuit 1 and the output data D031 of the sampled data storage circuit 4, and the output data D021 of the data addition circuit 2. As shown in FIG. 7, when the sampling-completed flag S011 is 0, the output data D031 of the sampled data storage circuit 4 is output as output data D021. When the sampling-completed flag S011 changes to 1, the addition value D121 of the output data D011 of the sampling circuit 1 at that time and of the output data D031 of the sampled data storage circuit 4 becomes the output data D021.
FIG. 8 shows, as time charts, the relations between the sampling-completed flag S011 input to the sampling command circuit 3, the sampling-start flag S021 output from the sampling command circuit 3, and the count value S133 of the counter 34 in the sampling command circuit 3. In response to the rising edge of the sampling-completed flag S011 from the sampling circuit 1, in the sampling command circuit 3 the output data S131 from AND circuit 31 is captured and stored in the storage circuit 33 in sync with the clock pulse, and is output as the flag data S132. When the sampling-completed flag S011 is 1, the flag data S132 indicating 1 is output via the AND circuit 32 as the sampling-start flag S021. In response to the rising edge of the flag data S132, the counter 34 begins counting up. When the count value S133 reaches the fixed value S134 (2M), the comparison output S135 flag of comparator 35 rises, and in response to the flag S135, output as the sampling-start flag S021 of the flag data S132 by the AND circuit 32 is interrupted, the counting-up of the counter 34 is halted, and the count value S133 is returned to the initial value.
FIG. 9 shows as time charts the relations between a clock pulse CK, the data D021 supplied to the sampled data storage circuit 4 from the data addition circuit 2, and the output data D031 and D041 from the sampled data storage circuit 4. At the rising edge of the clock pulse CK, the data D021 supplied from the data addition circuit 2 is stored by storage circuits 41[0] to 41[N+M−1], and become output data D031. The upper N bits (in FIG. 9, the upper 3 bits) of the output data D031 are the averaged output data D041.
2M elements of sampled data are added by the addition circuit 2 and stored in the sampled data storage circuit 4. As a result, the stored data becomes the sum of 2M elements of data. The result of dividing the value by 2M is an average value of the sampled data. Upon dividing by 2M, in binary notation, the result is obtained by deleting the lower M bits. The lower M bits become the remainder. Therefore, the values of storage circuits 41[N+M−1] to 41[M] in the sampled data storage circuit 4 become the average data of 2M elements of sampled data, with the lowest M bits discarded.
However, in the conventional sampled data averaging circuit, since the number of samples is fixed, and is not arbitrarily set, it is impossible to sample input data by an optimum number of sampling times in accordance with changes in the input data to average the sampled data.